A CMOS power-delay model for CAD optimization tools

被引：0

作者：

Delaurenti, M ^{[1
]}

Masera, G ^{[1
]}

Piccinini, G ^{[1
]}

Roch, MR ^{[1
]}

Zamboni, M ^{[1
]}

机构：

[1] Politecn Torino, Dipartimento Elettron, I-10129 Turin, Italy

来源：

IEEE ALESSANDRO VOLTA MEMORIAL WORKSHOP ON LOW-POWER DESIGN, PROCEEDINGS | 1999年

关键词：

D O I：

10.1109/LPD.1999.750405

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The need of fast and reliable models for CMOS gate has grown importance not only for the simulation digital VLSI circuits, but also for their optimization. In a library based design the optimum of speed is a basic step to achieve high performance, but also pourer consumption must be considered with increasing care. A simultaneous power-delay evaluation can be performed using a new model developed for sub-micron CMOS technologies, allowing better multi-objective optimization.

引用

页码：72 / 77

页数：6

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