共 50 条
[11]
A simulation-based power-aware architecture exploration of a multiprocessor system-on-chip design
[J].
DESIGNERS' FORUM: DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION,
2004,
:312-317
[12]
A real-time asymmetric multiprocessor reconfigurable system-on-chip architecture
[J].
MICROELECTRONICS: DESIGN, TECHNOLOGY, AND PACKAGING II,
2006, 6035
[15]
Interfacing UML 2.0 for multiprocessor System-on-Chip design flow
[J].
2005 INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP, PROCEEDINGS,
2005,
:108-111
[16]
A distributed airchitecture model for heterogeneous multiprocessor system-on-chip design
[J].
EMBEDDED SOFTWARE AND SYSTEMS,
2005, 3605
:150-157
[18]
An efficient bus architecture for system-on-chip design
[J].
PROCEEDINGS OF THE IEEE 1999 CUSTOM INTEGRATED CIRCUITS CONFERENCE,
1999,
:623-626
[20]
Efficient bus architecture for system-on-chip design
[J].
Proceedings of the Custom Integrated Circuits Conference,
1999,
:623-626