Integration of III-V nanowires on Si: From high-performance vertical FET to steep-slope switch

被引：0

作者：

Tomioka, Katsuhiro ^{[1
]}

Yoshimura, Masatoshi ^{[1
]}

Nakai, Eiji ^{[1
]}

Ishizaka, Fumiya ^{[1
]}

Fukui, Takashi ^{[1
]}

机构：

[1] Hokkaido Univ, Grad Sch Informat Sci & Technol, Sapporo, Hokkaido 0608628, Japan

来源：

2013 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2013年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we present recent progress in the integration of vertical III-V nanowire-channels on Si by selective-area epitaxy and demonstrations of high-performance III-V vertical surrounding-gate transistors with high-k dielectrics with an EOT of less than 1 nm, modulation doping technique, and challenges in steep subthreshold-slope switching using III-V nanowire/Si heterojunctions as building blocks for low power circuits.

引用

页数：4

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