Low power CMOS pass logic 4-2 compressor for high-speed multiplication

被引：0

作者：

Radhakrishnan, D ^{[1
]}

Preethy, AP ^{[1
]}

机构：

[1] SUNY Albany, Dept Elect & Comp Engn, New Paltz, NY 12561 USA

来源：

PROCEEDINGS OF THE 43RD IEEE MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I-III | 2000年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A novel CMOS 4-2 compressor using pass logic is presented in this paper. An XOR-XNOR combination gate is used to build the circuit while totally eliminating the use of inverters. The total power dissipation has been cut down to a minimum while providing the full output voltage swing at all nodes in the circuit. Furthermore, the complete circuit is implemented with a bare minimum of 28 transistors.

引用

页码：1296 / 1298

页数：3

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