Wide-range harmonic lock detector with real-time delay measurement of delay-locked loop

被引：1

作者：

Kim, Sangseob ^{[1
]}

Hyoung, Chang-Hee ^{[1
]}

Park, Kyoung-Hwan ^{[1
]}

机构：

[1] Elect & Telecommun Res Inst, SW SOC Convergence Res Lab, Taejon 305700, South Korea

来源：

ELECTRONICS LETTERS | 2015年 / 51卷 / 02期

关键词：

delay lock loops; CMOS integrated circuits; phase detectors; UHF integrated circuits; frequency 25 MHz to 500 MHz; CMOS technology; HLD; external reset control; delay indicators; DLL; delay-locked loop; real-time delay measurement; wide-range harmonic lock detector;

D O I：

10.1049/el.2014.3749

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new robust harmonic lock detector (HLD) suitable for a wide-range delay-locked loop (DLL) is presented. This detector is composed of some delay indicators measuring the total delay of the DLL in real time, and it can detect the harmonic lock for a wide frequency range close to 1-20 times higher than the minimum frequency. Owing to its seamless operation without any initialising process using external reset control, it can ensure reliable lock detection despite some unusual conditions, such as frequency change, electrical surge input or power-ground fluctuation. The proposed HLD and the DLL were designed in 0.13 mu m CMOS technology, and the simulation results showed the exact harmonic lock detection and reliable DLL locking properties over the whole frequency range from 25 to 500 MHz of the input clock.

引用

页码：136 / 137

页数：2

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