Lithography-simulation-based design for manufacturability rule development: an integrated circuit design house's approach

被引:3
|
作者
Ho, Jonathan
Wang, Yan
Wu, Joanne
Hou, Ya-Ching
Wu, Kechih
机构
[1] Xilinx Inc, San Jose, CA 95124 USA
[2] Anchor Semicond Inc, Santa Clara, CA 95054 USA
来源
JOURNAL OF MICRO-NANOLITHOGRAPHY MEMS AND MOEMS | 2007年 / 6卷 / 03期
关键词
design for manufacture; optical proximity correction; mask error enhancement factor; lithography;
D O I
10.1117/1.2781584
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We describe design house approaches for design rule developments with emphasis of valuations of pre-optical proximity correction (pre-OPC) layouts and their simulation results. To begin, we describe the procedure of the simulation model calibration. An evaluation of metrics for analyzing the design layouts is then described. Due to the unavailability of post-OPC layouts, both pre-OPC and trial-OPC simulations are studied. A range of layout pattern density, within which the pre-OPC metric follows the post-OPC's, is estimated. Within this pattern density range, pre-OPC layout then can be evaluated to identify potential process '' hot spots.'' With this approach, a set of design for manufacturability (DFM) compliance design rules is derived and applied to the product developments for both 90-and 65-nm process technology nodes. Several hot spots in the products (designed with 90-nm design rules) are located and fixed using layout optimization guided by the DFM rules. Simulated image contours and in-line scanning electron microscope (SEM) images validate the approach. (C) 2007 Society of Photo-Optical Instrumentation Engineers.
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页数:10
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