Survey of Memory, Timing, and Power Management Verification Methods for Multi-core Processors

Currently, the most significant challenge multicore design engineers face is improving the performance of multi-processors while decreasing the power consumption. Multi-core systems provide a good solution to the increasing high computing applications that need performance boost. However, a good multi-core processor requires thorough and efficient verification procedures. We present a survey on verification techniques for multi-core systems specifically targeting memory, timing, and power management schemes. For memory verification we look into structural simulation-based verification for register arrays, co-simulation techniques, threaded core memory model, symbolic trajectory evaluation for memory arrays, hardware logic emulation, graph model of cache hierarchy and assertion-based simulation schemes. Furthermore, we look into post-silicon verification techniques using the inverse of an instruction and a specific method called DACOTA. For timing verification, we cover three categories of verification: full integration, temporal isolation, and interference effects on schedulability. For dynamic power management schemes, we cover statistical model checking, probabilistic model checking, fractal design verification, and verification for schemes that are interwoven in hardware and software. These verification techniques are tested on the following power management schemes: dynamic voltage and frequency scaling, power gating, and fractal design.