A Unified Framework for Error Correction in On-Chip Memories

Many techniques have been proposed to improve the reliability of on-chip memories (e.g., caches). These techniques can be broadly characterized as being based on either error-correcting codes, side-information from built-in self test (BIST) routines, or hybrid combinations of the two. Although each proposal has been shown to be favorable under a certain set of assumptions and parameters, it is difficult to determine the suitability of such techniques in the overall design space. In this paper, we seek to resolve this problem by introducing a unified general framework representing such schemes. The framework, composed of storage, decoders, costs, and error rates, allows a full exploration of the design space of reliability techniques. We show how existing schemes can be represented in this framework and we use the framework to examine performance in the practical case of high overall and moderate BIST-undetectable fault rates. We show that erasure-based side-information schemes are less sensitive to BIST-undetectable errors compared to other techniques.