Development of Frequency-Fixed All-Pass Filter-Based Single-Phase Phase-Locked Loop

被引:29
作者
Gautam, Samir [1 ]
Xiao, Weidong [1 ]
Lu, Dylan Dah-Chuan [2 ]
Ahmed, Hafiz [3 ]
Guerrero, Josep M. [4 ]
机构
[1] Univ Sydney, Sch Elect & Informat Engn, Sydney, NSW 2006, Australia
[2] Univ Technol Sydney, Sch Elect & Data Engn, Sydney, NSW 2006, Australia
[3] Bangor Univ, Nucl Futures Inst, Bangor LL57 1UT, Gwynedd, Wales
[4] Aalborg Univ, Dept Energy Technol, DK-9220 Aalborg, Denmark
基金
澳大利亚研究理事会;
关键词
Phase locked loops; Power electronics; Harmonic analysis; Frequency locked loops; Steady-state; Voltage-controlled oscillators; Tuning; All-pass filter (APF); frequency-fixed (FF) orthogonal signal generation (OSG); grid-synchronization; phase-locked loop (PLL); DC-OFFSET REJECTION; PLL; DESIGN; TIME;
D O I
10.1109/JESTPE.2021.3085124
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Phase-locked loops (PLL) are widely used in the synchronization of grid interfaced power converters. One solution is based on orthogonal signal generation (OSG), which requires the grid frequency information for their appropriate operation. This article developed a new solution to achieve the PLL function for single-phase grid interconnection but eradicate additional frequency feedback loops in the traditional architecture of all-pass filter PLL (APF-PLL). Four new topologies are developed along with their small-signal modeling and dynamic analysis. A thorough comparison among them on their dynamic response, steady-state accuracy, implementation, and disturbance rejection capability is carried out. Finally, the best approach of frequency-fixed (FF) APF-PLL is experimentally evaluated with frequency adaptive APF-PLL and FF PLLs belonging to time delay (TD) and second-order generalized integrator (SOGI) families.
引用
收藏
页码:506 / 517
页数:12
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