The application of BT-FinFET technology for sub 60nm DRAM integration

被引：0
|
作者：
Lee, CH [1 ]
Yoon, JM [1 ]
Lee, C [1 ]
Kim, K [1 ]
Park, SB [1 ]
Ahn, YJ [1 ]
Kang, FS [1 ]
Park, D [1 ]
机构：
[1] Samsung Elect, Device Res Team, R&D Ctr, Yongin 449711, Gyeonggi Do, South Korea
来源：
2005 INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY | 2005年
关键词：
D O I：
10.1109/ICICDT.2005.1502585
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, the application of body tied FinFET is presented for a technology breakthrough beyond sub 60nm. DRAM on bulk Si substrate has been successfully integrated and the characteristics were compared to recess channel and planar cell array transistor DRAM. We present a comparison of three different device structures and show damascene BT-FinFET using NWL (Negative Word Line) scheme with low channel for a highly manufacturable DRAM for sub 60nm technology node.
引用
收藏
页码：37 / 41
页数：5
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