A mixed-mode delay-locked loop for wide-range operation and multiphase outputs

This paper describes a mixed-mode delay-locked loop (DLL) for wide-range operation and multiphase outputs with just one clock cycle. The architecture of the proposed DLL uses the time-to-digital converter (TDC) scheme for phase range selector to offer the faster locking time, and the multi-controlled delay cell for voltage-controlled delay line (VCDL) to provide the wide locked range and the low-jitter performance. The proposed DLL can solve the problem of false locking associated with conventional DLLs. The HSPICE simulation results are based upon TSMC 0.35mum 1P4M N-well CMOS process with a 3.3V power supply voltage. The simulation results show that the proposed DLL can operate from 62.5 to 312.5 MHz. Moreover, the total time delay from all delay stages is precisely one period of the input reference signal, and that can generate equally spaced ten-phase clocks.