A Compact Gated-Synapse Model for Neuromorphic Circuits

被引：3

作者：

Jones, Alexander ^{[1
]}

Jha, Rashmi ^{[1
]}

机构：

[1] Univ Cincinnati, Elect Engn & Comp Sci Dept, Cincinnati, OH 45220 USA

来源：

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 2021年 / 40卷 / 09期

基金：

美国国家科学基金会;

关键词：

Logic gates; Integrated circuit modeling; Computational modeling; Neuromorphics; Synapses; Threshold voltage; Transient analysis; Computer-aided design of gated-synaptic memory; neuromorphic circuit design; synapse model; Verilog-A; MEMRISTOR;

D O I：

10.1109/TCAD.2020.3028534

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This work reports a compact behavioral model for gated-synaptic memory. The model is developed in Verilog-A for easy integration into computer-aided design of neuromorphic circuits using emerging memory. The model encompasses various forms of gated synapses within a single framework and is not restricted to only a single type. The behavioral theory of the model is described in detail along with a full list of the default parameter settings. The model includes parameters, such as a device's ideal set time, threshold voltage, general evolution of the conductance with respect to time, decay of the device's state, etc. Finally, the model's validity is shown via extensive simulation and fitting to experimentally reported data on published gated-synapses.

引用

页码：1887 / 1895

页数：9

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