A 1.2 V 200-MS/s 10-bit folding and interpolating ADC in 0.13-μm CMOS

被引：6
|
作者：
Chen, Yihui [1 ]
Huang, Qiuting [1 ]
Burger, Thomas [1 ]
机构：
[1] ETH, Integrated Syst Lab, CH-8092 Zurich, Switzerland
来源：
ESSCIRC 2007: PROCEEDINGS OF THE 33RD EUROPEAN SOLID-STATE CIRCUITS CONFERENCE | 2007年
关键词：
D O I：
10.1109/ESSCIRC.2007.4430269
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents a folding and interpolating ADC in a 0.13-mu m CMOS technology, which achieves 10-bit resolution and 200-MS/s sample rate despite the limitations of a 1.2 V supply voltage. The converter employs an open-loop autozero technique to cancel preamplifier offsets, and preamplifiers provide sufficient gain to overcome offsets from the following stages, which enable 8.6 ENOB (53.5 dB SNDR) to be reached. The IC measures 3.24 mm(2) including pads and consumes 195 mW in total.
引用
收藏
页码：155 / 158
页数：4
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