Temperature study of sub-micrometric ICs by scanning thermal-microscopy

Surface temperature measurements were performed with a scanning thermal microscope mounted with a thermoresistive wire probe of micrometric size. A CMOS device was designed with arrays of resistive lines 0.35 mu m in width. The array periods are 0.8 mu m and 10 mu m to study the spatial resolution of the SThM. Integrated Circuits (ICs) with passivation layers of micrometric and nanometric thicknesses were tested. To enhance signal-to-noise ratio, the resistive lines were heated with an ac current. The passivation layer of nanometric thickness allows us to distinguish the lines when the array period is 10 mu m. The results raise the difficulties of the SThNI measurement due to the design and the topogm raphy of ICs on one hand and the size of the thermal probe on the other hand.