Carbon nanotube bumps for the flip chip packaging system

被引：23
|
作者：
Yap, Chin Chong [1 ,2 ]
Brun, Christophe [1 ,3 ]
Tan, Dunlin [1 ,2 ]
Li, Hong [2 ]
Teo, Edwin Hang Tong [1 ,2 ,4 ]
Baillargeat, Dominique [1 ]
Tay, Beng Kang [1 ,2 ]
机构：
[1] CINTRA CNRS NTU THALES, UMI 3288, Singapore 637553, Singapore
[2] Nanyang Technol Univ, Sch Elect & Elect Engn, Singapore, Singapore
[3] Univ Limoges, XLIM UMR 6172, CNRS, F-87060 Limoges, France
[4] Temasek Labs NTU, Singapore 637553, Singapore
来源：
NANOSCALE RESEARCH LETTERS | 2012年 / 7卷
关键词：
CNT bumps; interconnects; flip chip; packaging; GROWTH-PROCESS;
D O I：
10.1186/1556-276X-7-105
中图分类号：
TB3 [工程材料学];
学科分类号：
0805 ; 080502 ;
摘要：
Carbon nanotube [CNT] interconnection bump joining methodology has been successfully demonstrated using flip chip test structures with bump pitches smaller than 150 mu m. In this study, plasma-enhanced chemical vapor deposition approach is used to grow the CNT bumps onto the Au metallization lines. The CNT bumps on the die substrate are then 'inserted' into the CNT bumps on the carrier substrate to form the electrical connections (interconnection bumps) between each other. The mechanical strength and the concept of reworkable capabilities of the CNT interconnection bumps are investigated. Preliminary electrical characteristics show a linear relationship between current and voltage, suggesting that ohmic contacts are attained.
引用
收藏
页码：1 / 8
页数：8
相关论文
共 50 条
  • [41] Flip chip assembly on PCB substrates with coined solder bumps
    Nah, JW
    Paik, KW
    Cho, SJ
    Kim, WH
    53RD ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, 2003 PROCEEDINGS, 2003, : 244 - 249
  • [42] Flip chip bonding technique using transferred microsolder bumps
    NTT Optoelectronics Lab, Tokyo, Japan
    IEEE transactions on components, packaging and manufacturing technology. Part C. Manufacturing, 1997, 20 (04): : 327 - 334
  • [43] Failure analysis of flip chip bumps after thermal stressing
    Hooghan, TK
    Hooghan, K
    Nakahara, S
    Wolf, RK
    Privette, RW
    Moyer, RS
    ISTFA 2000: PROCEEDINGS OF THE 26TH INTERNATIONAL SYMPOSIUM FOR TESTING AND FAILURE ANALYSIS, 2000, : 41 - 48
  • [44] Outperformance of Cu Pillar Flip Chip Bumps in Electromigration Testing
    Labie, Riet
    Dosseul, Franck
    Webers, Tomas
    Winters, Christophe
    Cherman, Vladimir
    Beyne, Eric
    Vandevelde, Bart
    2011 IEEE 61ST ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2011, : 312 - 316
  • [45] Reliability investigations of flip-chip solder bumps on palladium
    Kallmayer, C
    Oppermann, H
    Anhöck, S
    Klein, M
    Kalicki, R
    Aschenbrenner, R
    Reichl, H
    49TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE - 1999 PROCEEDINGS, 1999, : 135 - 140
  • [46] Carbon nanotube bumps for LSI interconnect
    Soga, Ikuo
    Kondo, Daiyu
    Yamaguchi, Yoshitaka
    Twai, Taisuke
    Mizukoshi, Masataka
    Awano, Yuji
    Yube, Kunio
    Fujii, Takashi
    58TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, PROCEEDINGS, 2008, : 1390 - +
  • [47] Flip chip chip scale packaging: Transfering the flip chip density requirements from the motherboard to the chip carrier
    Aday, JG
    Koehler, C
    Tessier, T
    Carpenter, B
    Matsuda, Y
    Estes, C
    1998 INTERNATIONAL CONFERENCE ON MULTICHIP MODULES AND HIGH DENSITY PACKAGING, PROCEEDINGS, 1998, : 229 - 235
  • [48] Diagnosing and avoiding flip chip packaging defects
    Adams, T
    EE-EVALUATION ENGINEERING, 2001, 40 (05): : 92 - +
  • [49] Advances and challenges in flip-chip packaging
    Mahajan, R.
    Mallik, D.
    Sankman, R.
    Radhakrishnan, K.
    Chiu, C.
    He, J.
    PROCEEDINGS OF THE IEEE 2006 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2006, : 703 - 709
  • [50] Characterization of OSP for flip chip PBGA packaging
    Wetz, LA
    Kirschenbaum, K
    Kalisz, S
    PAN PACIFIC MICROELECTRONICS SYMPOSIUM, 2001, PROCEEDINGS, 2001, : 475 - 483
12345