A Low-Power Level Shifter With Logic Error Correction for Extremely Low-Voltage Digital CMOS LSIs

被引:89
作者
Osaki, Yuji [1 ]
Hirose, Tetsuya [1 ]
Kuroki, Nobutaka [1 ]
Numa, Masahiro [1 ]
机构
[1] Kobe Univ, Dept Elect & Elect Engn, Nada Ku, Kobe, Hyogo 6578501, Japan
关键词
Level converter; level shifter; low power; low voltage; subthreshold; SUBTHRESHOLD;
D O I
10.1109/JSSC.2012.2191320
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents a level shifter circuit capable of handling extremely low-voltage inputs. The circuit has a distinctive current generation scheme using a logic error correction circuit that works by detecting the input and output logic levels. The proposed level shifter circuit can convert low-voltage digital input signals into high-voltage digital output signals. The circuit achieves low-power operation because it dissipates operating current only when the input signal changes. Measurement results demonstrated that the circuit can convert a 0.23-V input signal into a 3-V output signal. The power dissipation was 58 nW for a 0.4-V 10-kHz input pulse.
引用
收藏
页码:1776 / 1783
页数:8
相关论文
共 15 条
[1]  
[Anonymous], 2007, POWER MANAGEMENT DIG
[2]   Level converters with high immunity to power-supply bouncing for high-speed sub-1-V LSIs [J].
Kanno, Y ;
Mizuno, H ;
Tanaka, K ;
Watanabe, T .
2000 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2000, :202-203
[3]   Fast-delay and low-power level shifter for low-voltage applications [J].
Kwon, O-Sam ;
Min, Kyeong-Sik .
IEICE TRANSACTIONS ON ELECTRONICS, 2007, E90C (07) :1540-1543
[4]   A Subthreshold to Above-Threshold Level Shifter Comprising a Wilson Current Mirror [J].
Luetkemeier, Sven ;
Rueckert, Ulrich .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2010, 57 (09) :721-724
[5]   Nanosecond Delay Floating High Voltage Level Shifters in a 0.35 μm HV-CMOS Technology [J].
Moghe, Yashodhan ;
Lehmann, Torsten ;
Piessens, Tim .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2011, 46 (02) :485-497
[6]  
Osaki Y., 2011, 37th European Solid State Circuits Conference (ESSCIRC 2011), P199, DOI 10.1109/ESSCIRC.2011.6044899
[7]  
Osaki Y., 2011, 2011 IEEE 9th International New Circuits and Systems Conference (NEWCAS 2011), P201, DOI 10.1109/NEWCAS.2011.5981290
[8]   MATCHING PROPERTIES OF MOS-TRANSISTORS [J].
PELGROM, MJM ;
DUINMAIJER, ACJ ;
WELBERS, APG .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1989, 24 (05) :1433-1440
[9]   A robust, input voltage adaptive and low energy consumption level converter for sub-threshold logic [J].
Shao, Hui ;
Tsui, Chi-Ying .
ESSCIRC 2007: PROCEEDINGS OF THE 33RD EUROPEAN SOLID-STATE CIRCUITS CONFERENCE, 2007, :312-315
[10]  
Taur Y., 2002, FUNDAMENTALS MODERN