共 24 条
- [1] [Anonymous], 2011, IEEE INT C EMERGING, DOI DOI 10.1109/ETFA.2011.6058984
- [2] AutomationML Consortium, 2006, AUTOMATIONML
- [3] SysML Models Verification and Validation in an Industrial Context: Challenges and Experimentation [J]. MODELLING FOUNDATIONS AND APPLICATIONS (ECMFA 2018), 2018, 10890 : 132 - 146
- [5] On the Reuse of Heterogeneous IPs into SysML Models for Integration Validation [J]. JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2013, 29 (05): : 647 - 667
- [6] Danny P, 2017, IEEE INTL CONF IND I, P849, DOI 10.1109/INDIN.2017.8104883
- [7] Debbabi M, 2010, VERIFICATION AND VALIDATION IN SYSTEMS ENGINEERING: ASSESSING UML/SYSML DESIGN MODELS, P1, DOI 10.1007/978-3-642-15228-3_1
- [8] Drath R., 2012, P 2012 IEEE 17 INT C, P1, DOI DOI 10.1109/ETFA.2012.6489783
- [10] Friedenthal S., 2014, A Practical Guide to SysML The Systems Modeling Language, V3rd ed., DOI DOI 10.1016/C2013-0-14457-1