Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects

被引:149
作者
Ajami, AH
Banerjee, K
Pedram, M
机构
[1] Univ So Calif, Dept Elect Engn & Syst, Los Angeles, CA 90089 USA
[2] Univ Calif Santa Barbara, Dept Elect & Comp Engn, Santa Barbara, CA 93106 USA
关键词
clock skew; Elmore delay; global interconnects; hot-spots; on-chip temperature variations; signal integrity; substrate thermal gradient;
D O I
10.1109/TCAD.2005.847944
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Nonuniform thermal profiles on the substrate in high-performance ICs can significantly impact the performance of global on-chip interconnects. This paper presents a detailed modeling and analysis of the interconnect performance degradation due to the nonuniform temperature profiles that are encountered along long metal interconnects as a result of existing thermal gradients in the underlying Silicon substrate. A nonuniform temperature-dependent distributed RC interconnect delay model is proposed. The model is applied to a wide variety of interconnect layouts and substrate temperature distributions to quantify the impact of such thermal nonuniformities on signal integrity issues including speed degradation in global interconnect lines and skew fluctuations in clock signal distribution networks. Subsequently, a new thermally dependent zero-skew clock-routing methodology is presented. This study suggests that thermally aware analysis should become an integrated part of the various optimization steps in physical-synthesis flow to improve the performance and integrity of signals in global ultra large scale integration interconnects.
引用
收藏
页码:849 / 861
页数:13
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