All-Digital Phase-Locked Loop in 40 nm CMOS for 5.8 Gbps Serial Link Transmitter

被引：0

作者：

Antonov, Yury ^{[1
]}

Tikka, Tero ^{[1
]}

Stadius, Kari ^{[1
]}

Ryynanen, Jussi ^{[1
]}

机构：

[1] Aalto Univ, Dept Micro & Nanosci, POB 13000, Espoo 02150, Finland

来源：

2015 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN (ECCTD) | 2015年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes an all-digital phase-locked loop based clock generator for a MIPI M-PHY serial link transmitter. The paper focuses on ADPLL phase accumulator speed optimization, PVT calibration, loop type changing criteria and power saving in phase digitization process. The experimental circuit is implemented in 40 nm CMOS and generates the MIPI M-PHY defined frequencies from 1.2 GHz to 5.8 GHz.

引用

页码：324 / 327

页数：4

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