A crystal-based low-voltage all-digital programmable ring oscillator

We have designed and implemented a flexible programmable multi-channel digitally-controlled oscillator (MDCO) on an Altera MAX9400 Complex Programmable Logic Device (CPLD) chip. Based on elaborate experiments with the system, we have developed techniques by which to improve its linearity, resolution and stability in an improved MDCO design. This new architecture is programmable to oscillate from 0 Hz to a maximum that is determined by the oscillator master processing clock and the technology limitations. As crystal-based-programmable-delay cells (CBPDC) control its dominant propagation delay, the oscillator frequency thermal drift and qjitter are reduced. In a complementary parallel development, to design high-speed and low-power sub-systems for high-speed applications, we have designed high-speed DCO and MDCOs by using the parameters of TSMC 0.25 um CMOS process with level 49 HSPICE models. At 3.3 Volts, the oscillation frequency has been increased up to 315 MHz in our ASIC MDCO design by using dynamic high-speed data flip-flops. In terms of specific applications, this architecture is suitable for digital wireless transceivers that use different bands for their transmit and receive modes, such as GSM and DECT. Yet to further enhance the operation of our DCOs, we have developed a new design technique by which to allow these blocks to operate at extremely low supply voltages. We have named this after IBM's work (Assaderaghi et al., IEDM Transactions, vol. 44, 414-422, March 1997) as DTMOS-like design style. Here, we use gate-bulk connected PMOS devices each in a separate Nwell to bring the PMOS-device threshold voltage further lower for operation with one Volt and below supplies. A wide-band 123 MHz, 0. 6 mW @ 1 V DCO core is designed and simulated in the same 0.25 um CMOS process.