A 16-bit 12-GS/s Single-/Dual-Rate DAC With a Successive Bandpass Delta-Sigma Modulator Achieving <-67-dBc IM3 Within DC to 6-GHz Tunable Passbands

被引:22
作者
Su, Shiyu [1 ]
Chen, Mike Shuo-Wei [1 ]
机构
[1] Univ Southern Calif, Dept Elect Engn Electrophys, Los Angeles, CA 90089 USA
关键词
5G communications; bandpass delta-sigma modulator (DSM); digital-to-analog converter; digital pre-distortion (DPD); high resolution; high speed; hybrid; RF; time interleaving; timing errors; tunable passbands; RADIO; SFDR; GHZ; DBC;
D O I
10.1109/JSSC.2018.2871143
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents a hybrid digital-to-analog converter (DAC) architecture with a tunable bandpass delta-sigma modulator (DSM) to synthesize channelized signals over a wide frequency range with high linearity and a low in-band noise floor. Due to the mostly digital architecture, this DAC topology favors technology scaling. The DSM uses a successive pipeline structure with time-interleaving techniques to achieve a 12-GS/s data rate and overall 16-bit DAC resolution. To improve the linearity at high frequencies, an inverse-sinc-shaped digital pre-distortion (DPD) scheme is used to better approximate and compensate the timing errors. The DAC can be configured for single- or dual-rate operation modes to tradeoff different input data rates with DAC linearity and spectral images. The prototype was fabricated in 65-nm CMOS technology with an analog area of 0.1 mm(2) and <250-mW analog power consumption. It achieved IM3 of -85 to -67 dBc over the Nyquist band, and the spurious-free dynamic range remains >60 dBc up to a 4.2-GHz signal frequency at 12 GS/s in the single-rate mode thanks to the hybrid structure and proposed DPD techniques.
引用
收藏
页码:3517 / 3527
页数:11
相关论文
共 21 条
  • [1] A Wideband RF Mixing-DAC Achieving IMD &lt;-82 dBc Up to 1.9 GHz
    Bechthum, Elbert
    Radulov, Georgi I.
    Briaire, Joost
    Geelen, Govert J. G. M.
    van Roermund, Arthur H. M.
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2016, 51 (06) : 1374 - 1384
  • [2] An 11 GS/s 1.1 GHz Bandwidth Interleaved ΔΣ DAC for 60 GHz Radio in 65 nm CMOS
    Bhide, Ameya
    Alyandpour, Atila
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2015, 50 (10) : 2306 - 2318
  • [3] Erdmann C, 2017, ISSCC DIG TECH PAP I, P280, DOI 10.1109/ISSCC.2017.7870370
  • [4] An All-Digital RF Signal Generator Using High-Speed ΔΣ Modulators
    Frappe, Antoine
    Flament, Axel
    Stefanelli, Bruno
    Kaiser, Andreas
    Cathelin, Andreia
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2009, 44 (10) : 2722 - 2732
  • [5] A wideband ΔΣ digital-RF modulator for high data rate transmitters
    Jerng, Albert
    Sodini, Charles G.
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2007, 42 (08) : 1710 - 1722
  • [6] Jianhong Xiao, 2013, 2013 Symposium on VLSI Circuits, pC262
  • [7] Lin CH, 2018, ISSCC DIG TECH PAP I, P360, DOI 10.1109/ISSCC.2018.8310333
  • [8] A 12 bit 2.9 GS/s DAC With IM3 &lt;-60 dBc Beyond 1 GHz in 65 nm CMOS
    Lin, Chi-Hung
    van der Goes, Frank M. L.
    Westra, Jan R.
    Mulder, Jan
    Lin, Yu
    Arslan, Erol
    Ayranci, Emre
    Liu, Xiaodong
    Bult, Klaas
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2009, 44 (12) : 3285 - 3293
  • [9] Radio frequency digital-to-analog converter
    Luschas, S
    Schreier, R
    Lee, HS
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2004, 39 (09) : 1462 - 1467
  • [10] 2.5-GHz, 6.9-mW, 45-nm-LP CMOS, ΔΣ Modulator Based on Standard Cell Design With Time-Interleaving
    Madoglio, Paolo
    Ravi, Ashoke
    Cuellar, Luis
    Pellerano, Stefano
    Seddighrad, Parmoon
    Lomeli, Ismael
    Palaskas, Yorgos
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2010, 45 (07) : 1410 - 1420