High breakdown voltage CMOS transistor with intrinsic SOI substrate

被引：0

作者：

Yamaguchi, H ^{[1
]}

Akita, S ^{[1
]}

Himi, H ^{[1
]}

Kawamoto, K ^{[1
]}

机构：

[1] Denso Corp, Res Labs, Aichi 4700011, Japan

来源：

SEMICONDUCTOR WAFER BONDING: SCIENCE, TECHNOLOGY, AND APPLICATIONS V, PROCEEDINGS | 2001年 / 99卷 / 35期

关键词：

D O I：

暂无

中图分类号：

O646 [电化学、电解、磁化学];

学科分类号：

081704 ;

摘要：

A new method for electric field relaxation in power device by using intrinsic SOI substrate was proposed. It was revealed by device simulation that this idea is effective to achieve both high breakdown voltage and high packing density for both Nch and Pch device. Furthermore, by fabricating both Nch low side switch and Pch high side switch on intrinsic SOI substrate, breakdown voltage more than 250V and output drain current of 30mA per 800 mum gate width were achieved.

引用

页码：459 / 469

页数：5