A CMOS transceiver for 10-Mb/s and 100-Mb/s Ethernet

被引：21

作者：

Everitt, J

Parker, JF

Hurst, P

Nack, D

Konda, KR

机构：

[1] Level One Commun, Sacramento, CA 95827 USA

[2] Univ Calif Davis, Dept Elect & Comp Engn, Davis, CA 95616 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1998年 / 33卷 / 12期

关键词：

analog processing circuits; data communication; local-area networks; mixed analog-digital integrated circuits;

D O I：

10.1109/4.735701

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A CMOS IC that implements the 802.3 Ethernet standards for 10- and 100-Mb/s data rates is described. The circuit uses mixed-signal techniques to perform transmit pulse shaping, receive adaptive line equalization, baseline wander compensation, and timing recovery. The IC occupies 23 mm(2) in a 0.6-mu m single-poly CMOS process and dissipates 850 mW from a 5-V supply.

引用

页码：2169 / 2177

页数：9