An SVPWM Method for Parallel Resonant DC-Link Inverter With the Smallest Loss in the Auxiliary Commutation Circuit

In order to reduce the operating frequency and loss of the auxiliary commutation circuit (ACC) and current stress of auxiliary switches of a parallel resonant dc-link inverter (PRDCLI), this article proposes a novel space vector pulsewidth modulation (SVPWM) method. The novel SVPWM method can reduce the number of operations of the ACC to once in every PWM cycle on the premise of realizing soft switching of all switches, thereby reducing the operating frequency and loss of the ACC. At the same time, by adding the shunt dead time, the novel SVPWM method can avoid the superposition of the resonant current and load current, thereby minimizing the current stress of auxiliary switches. In addition, the novel SVPWM method can apply to any PRDCLI with the ability of variable zero voltage durations. Under the novel SVPWM method, according to the equivalent circuits of different operation modes, the operation principle, soft switching realization conditions and parameter design methods of the inverter are analyzed. Finally, a 10-kW/16-kHz prototype is built using insulated gate bipolar transistors to verify the validity of the novel SVPWM method.