A robust 130 nm-CMOS built-in current sensor dedicated to RF applications

被引:7
作者
Cimino, M. [1 ]
Lapuyade, H. [1 ]
De Matos, M. [1 ]
Taris, T. [1 ]
Deval, Y. [1 ]
Begueret, J. B. [1 ]
机构
[1] Univ Bordeaux 1, IMS Lab, Talence, France
来源
JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS | 2007年 / 23卷 / 06期
关键词
design for testability; built-in current sensor; analog and mixed-signal integrated circuits; CMOS technology; robustness;
D O I
10.1007/s10836-007-5025-3
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper we present a design methodology that allows a dramatic reduction of the dependency on process variation, yielding to a new version of this BICS. Taking advantage of a 130 nm VLSI CMOS technology, the proposed BICS has a peak-to-peak dispersion lower than 10% of its output full-scale range. It makes it more suitable to implement the test functionality while maintaining the initial BICS intrinsic performances. The built-in self-test methodology is illustrated by monitoring the supply current of Low-Noise Amplifiers (LNAs). Measurements confirm the BICS's transparency relative to the circuit-under-test (CUT) and its accuracy.
引用
收藏
页码:593 / 603
页数:11
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