Optimized VLSI design of wavelet transform architecture

This paper presents a VLSI implementation of One Dimensional Direct Discrete Wavelet transform. We propose a new architecture using parallel filters. We consider the implementation of 1-D three levels DWT. The proposed architecture is simple and offers 16-bit precision on input and output data. No memory or registers are used for storing intermediate results. The end result is an efficient VLSI implementation with a reduced area cost compared to the conventional approaches. The architecture can compute DWT at a data rate of 7 x 10(6) samples/s corresponding to a typical clock speed of 7 MHz with 3.2V of operate voltage. Process parameters used were those of 0.35 mu m technology. The chip area is about 2 mm(2).