A Drift-Tolerant Read/Write Scheme for Multilevel Memristor Memory

Memristor based crossbar memories are prime candidates to succeed the Flash as the mainstream nonvolatile memory due to their density, scalability, write endurance and capability of storing multibit per cell. In this paper, we present a memristor crossbar memory architecture that utilizes a reduced constraint read-monitored-write scheme. The proposed scheme supports multibit storage per cell and utilizes reduced hardware, aiming to decrease the feedback complexity and latency while still operating with CMOS compatible voltages. We additionally present a read technique that can successfully distinguish resistive states under the existence of resistance drift due to read/write disturbances in the array. We also provide derivations of analytical relations to set forth a design methodology in selecting peripheral device parameters.