A 12-bit Domino ADC with a Background Offset Calibration Scheme

被引：0

作者：

Chung, Yung-Hui ^{[1
]}

机构：

[1] Natl Taiwan Univ Sci & Technol, Dept Elect & Comp Engn, Taipei, Taiwan

来源：

2019 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2019) | 2019年

关键词：

analog-to-digital conversion (ADC); offset calibration; digital-to-analog conversion (DAC); domino ADC; successive-approximation; SAR ADC; 6-BIT;

D O I：

10.1109/apccas47518.2019.8953171

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This study presents a background offset calibration scheme for domino analog-to-digital converters (ADCs). The domino ADC uses more-than-one comparators to achieve both high-speed and low-power operation. The offset deviation among comparators must be mitigated to improve the effective number of bits (ENOB). This helps the resolution of the domino ADC to be improved from 6-bit to 10/12-bit. In the domino ADC, each comparator acts as both a quantizer and a DAC controller. Therefore, the operation speed can be faster than successive-approximation-register ADCs. In this study, using the proposed offset calibration scheme on a 12-bit domino ADC, the worst ENOB is improved from 7.2b to 11.87b.

引用

页码：9 / 12

页数：4

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