A 86 MHz-12 GHz Digital-Intensive PLL for Software-Defined Radios, Using a 6 fJ/Step TDC in 40 nm Digital CMOS

被引：47

作者：

Borremans, Jonathan ^{[1
]}

Vengattaramane, Kameswaran ^{[1
]}

Giannini, Vito ^{[1
]}

Debaillie, Bjoern ^{[1
]}

Van Thillo, Wim ^{[1
]}

Craninckx, Jan ^{[1
]}

机构：

[1] IMEC, B-3001 Louvain, Belgium

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2010年 / 45卷 / 10期

关键词：

Background calibration; CMOS; DAC; digital-intensive; digital phase modulation; digital-to-analog converter; fractional-N; PLL; TDC; time-to-digital converter; 40; nm; RING OSCILLATOR; 90-NM CMOS; BAND VCO; CONVERTER; RECEIVER; NOISE; TRANSMITTER; PATH;

D O I：

10.1109/JSSC.2010.2063630

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 86 MHz-12 GHz digital-intensive reconfigurable PLL frequency synthesizer is presented with 100 kHz to 2 MHz bandwidth. It leverages a 6 fJ/ step 5.5 ps, 14b coarse-fine TDC and a 6-12 GHz dual-VCO set. Several simple calibration schemes are proposed that enable the proper performance of the highly efficient TDC in the PLL. The 0.28 mm(2) synthesizer, which is appropriate for use in a Software-Defined Radio, features Delta Sigma noise cancellation and digital phase modulation and consumes less than 30 mW.

引用

页码：2116 / 2129

页数：14

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