CGRA-ME: An Open-Source Framework for CGRA Architecture and CAD Research (Invited Paper)

被引:22
作者
Anderson, Jason [1 ]
Beidas, Rami [1 ]
Chacko, Vimal [1 ]
Hsiao, Hsuan [1 ]
Ling, Xiaoyi [1 ]
Ragheb, Omar [1 ]
Wang, Xinyuan [1 ]
Yu, Tianyi [1 ]
机构
[1] Univ Toronto, Dept Elect & Comp Engn, Toronto, ON, Canada
来源
2021 IEEE 32ND INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS (ASAP 2021) | 2021年
关键词
D O I
10.1109/ASAP52443.2021.00030
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Coarse-grained reconfigurable arrays (CGRAs) are programmable hardware platforms that can be used to realize application-specific accelerators for higher performance and energy efficiency. A CGRA is a 2D array of configurable logic blocks & interconnect, where the logic blocks are typically large & ALU-like, and the interconnect is word-wide. CGRA-ME is a software framework that enables the modelling and exploration of CGRA architectures, as well as research on CGRA CAD algorithms. With CGRA-ME, an architect can specify a CGRA architecture al a high level of abstraction. A set of applications can be mapped onto the architecture to assess the mappability, power, performance and cost. CGRA-ME also allows one to generate synthesizable Verilog RTL for the modelled CGRA, permitting its implementation as an ASIC or FPGA overlay. In this paper. we describe the CGRA-ME framework [5] and overview its capabilities and current limitations. We discuss ongoing and prior research conducted with the framework, as well as outline future plans. We believe CGRA-ME will be a valuable contribution to the community, enabling new research on CGRA CAD & architectures.
引用
收藏
页码:156 / 162
页数:7
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