Design of a Digital IP for 3D-IC die-to-die Clock Synchronization

被引：0

作者：

Sadi, Mehdi ^{[1
,2
]}

Kannan, Sukeshwar ^{[1
]}

England, Luke ^{[1
]}

Tehranipoor, Mark ^{[2
]}

机构：

[1] GLOBALFOUNDRIES, Malta, NY 12020 USA

[2] Univ Florida, Dept Elect & Comp Engn, Gainesville, FL 32611 USA

来源：

2017 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2017年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper the design of a novel IP for 3D IC die-to-die clock synchronization is presented. The proposed design offers notable benefits over the conventional dual DLL based architectures for 3D IC clock synchronization. Simulation results of the IP are presented with GLOBALFOUNDRIES 14nm finFET library, and Through-Silicon Via (TSV) technology.

引用

页码：714 / 717

页数：4

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