Failure analysis of 650 V enhancement mode GaN HEMT after short circuit tests

The paper presents the results of a post failure analysis performed on commercial 650 V GaN power HEMT after short circuit destructive tests. The used experiment set up includes a protection circuit able to avoid the explosion of the sample during the test. Moreover, it limits the energy involved in the failure and facilitates the identification of the areas where the failure is initiated. The post failure analysis confirms that DUTs exhibit two kinds of failures. In the first failure mode, for which large energies are dissipated in the device before the failure, the damaged area of the chip is quite large and is located close to external drain contacts. In this area, very likely, the temperature exceeds the melting temperature of the metallization. The second failure mode is observed for higher values of the drain voltage and involves lower energies dissipated in the DUT during SC before the failure. In this case, the damaged area is very small and is located below the source field plate at gate edge on the drain side. 2D finite element simulations show that in this region the dissipated power density becomes very high and can cause the local temperature to exceed the temperature limit of GaN/AIGaN structure.