Variation in transistor performance and leakage in nanometer-scale technologies

被引：76

作者：

Saxena, Sharad ^{[1
]}

Hess, Christopher ^{[1
]}

Karbasi, Hossein ^{[1
]}

Rossoni, Angelo ^{[1
]}

Tonello, Stefano ^{[1
]}

McNamara, Patrick ^{[1
]}

Lucherini, Silvia ^{[1
]}

Minehane, Sean ^{[1
]}

Dolainsky, Christoph ^{[1
]}

Quarantelli, Michele ^{[1
]}

机构：

[1] PDF Solut Inc, San Jose, CA 95110 USA

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2008年 / 55卷 / 01期

关键词：

design for manufacturability (DFM); semiconductor device variation; tolerance analysis; yield estimation; yield optimization;

D O I：

10.1109/TED.2007.911351

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Variation in transistor characteristics is increasing as CMOS transistors are scaled to nanometer feature sizes. This increase in transistor variability poses a serious challenge to the cost-effective utilization of scaled technologies. Meeting this challenge requires comprehensive and efficient approaches for variability characterization, minimization, and mitigation. This paper describes an efficient infrastructure for characterizing the various types of variation in transistor characteristics. A sample of results obtained from applying this infrastructure to a number of technologies at the 90-, 65-, and 45-nm nodes is presented. This paper then illustrates the impact of the observed variability on SRAM, analog and digital circuit blocks used in system-on-chip designs. Different approaches for minimizing transistor variation and mitigating its impact on product performance and yield are also described.

引用

页码：131 / 144

页数：14

共 59 条

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