Fabrication Method of Sub-100 nm Metal-Oxide-Semiconductor Field-Effect Transistor with Thick Gate Oxide

被引：5

作者：

Singh, Vipul ^{[1
]}

Inokawa, Hiroshi ^{[1
]}

Endoh, Tetsuo ^{[2
]}

Satoh, Hiroaki ^{[1
]}

机构：

[1] Shizuoka Univ, Elect Res Inst, Hamamatsu, Shizuoka 4328011, Japan

[2] Tohoku Univ, Interdisciplinary Res Ctr, Sendai, Miyagi 9808578, Japan

来源：

JAPANESE JOURNAL OF APPLIED PHYSICS | 2010年 / 49卷 / 12期

关键词：

MOSFET;

D O I：

10.1143/JJAP.49.128002

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

Based on the standard large-scale integrated circuit (LSI) process, sub-100 nm gate metal-oxide-semiconductor field-effect transistor (MOSFET) with thick gate oxide was fabricated. This was realized only by the modification of layout design, and no customization of the fabrication process was necessary. This unique designing technique is of great use in obtaining low-input-leakage MOSFET by advanced LSI process for high-performance analog applications. (C) 2010 The Japan Society of Applied Physics

引用

页数：2

共 50 条

[21] AN ANALYTICAL MODEL FOR THE INVERSE NARROW-GATE EFFECT OF A METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR
HONG, KM
CHENG, YC
JOURNAL OF APPLIED PHYSICS, 1987, 61 (06) : 2387 - 2392
[22] The demonstration of the magnetic Ge metal-oxide-semiconductor field-effect transistor
Liao, M. -H.
Huang, S. -C.
AIP ADVANCES, 2015, 5 (02):
[23] Probing the density of states in a metal-oxide-semiconductor field-effect transistor
Calvet, L. E.
Snyder, J. P.
Wernsdorfer, W.
PHYSICAL REVIEW B, 2008, 78 (19)
[24] Validity of mobility universality for scaled metal-oxide-semiconductor field-effect transistors down to 100 nm gate length
Matsumoto, S
Hisamitsu, K
Tanaka, M
Ueno, H
Miura-Mattausch, M
Mattausch, HJ
Kumashiro, S
Yamaguchi, T
Odanaka, S
Nakayama, N
JOURNAL OF APPLIED PHYSICS, 2002, 92 (09) : 5228 - 5232
[25] CHARACTERISTICS OF TIN GATE METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTORS
WITTMER, M
NOSER, JR
MELCHIOR, H
JOURNAL OF APPLIED PHYSICS, 1983, 54 (03) : 1423 - 1428
[26] A unified functional reliability model for N-channel metal-oxide-semiconductor field-effect transistors with sub 2 nm gate oxide
Lee, Hai-Ming
Du, Long-Jye
Liang, Mong-Song
King, Ya-Ching
Hsu, Charles Ching-Hsiang
Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, 2002, 41 (09): : 5546 - 5550
[27] A unified functional reliability model for N-channel metal-oxide-semiconductor field-effect transistors with sub 2 nm gate oxide
Lee, HM
Du, LJ
Liang, MS
King, YC
Charles, CLM
Hsu, CCH
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2002, 41 (09): : 5546 - 5550
[28] Simple and accurate method of modeling gate current of n-channel metal-oxide-semiconductor field-effect transistor
Yeh, Chun-Chia
Neih, Chun-Feng
Chen, Yen-Yu
Gong, Jeng
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2007, 46 (8A): : 5133 - 5135
[29] Simple and accurate method of modeling gate current of N-channel metal-oxide-semiconductor field-effect transistor
Yeh, Chun-Chia
Neih, Chun-Feng
Chen, Yen-Yu
Gong, Jeng
Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, 2007, 46 (8 A): : 5133 - 5135
[30] Gate technology for 70 nm metal-oxide-semiconductor field-effect transistors with ultrathin (<2 nm) oxides
J Vac Sci Technol B, 6 (2799):

← 1 2 3 4 5 →