Analysis of current-mode flip-flops in CMOS technologies

被引：0

作者：

Jiménez, R ^{[1
]}

Parra, P ^{[1
]}

Sanmartín, PM ^{[1
]}

Acosta, AJ ^{[1
]}

机构：

[1] IMSE CNM, Seville 41012, Spain

来源：

VLSI CIRCUITS AND SYSTEMS | 2003年 / 5117卷

关键词：

low-noise logic; current-mode circuits; submicron CMOS VLSI; mixed analog/digital; flip-flop design;

D O I：

10.1117/12.498978

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, the analysis of different implementations of memory elements-edge-triggered flip-flops, in current-mode technologies is presented. Main parameters as area, delay, power consumption and noise generation have been measured by electrical simulation in a 0.35 mum CMOS technology. The reliability in operation has been also quantified by timing violation parameters measurement. The main results obtained are, on one hand, the selection of a logic family for an specific application and, on the other hand, the selection of an specific flip-flop structure for a optimized parameter option power, noise or speed. Variations of measured parameters for different operation conditions have been also considered. The main results have shown that CBL-Current Balanced Logic-family presents the best behaviour.

引用

页码：515 / 526

页数：12

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