A platform based bus-interleaved architecture for de-blocking filter in H.264/MPEG-4 AVC

被引:33
作者
Chang, SC [1 ]
Peng, WH
Wang, SH
Chiang, T
机构
[1] Natl Chiao Tung Univ, Inst Elect, Hsinchu 30039, Taiwan
[2] Natl Chiao Tung Univ, Inst Elect Engn, Hsinchu, Taiwan
关键词
H.264 de-blocking filter; loop filter; AVC;
D O I
10.1109/TCE.2005.1405728
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, we proposed a platform based bus-interleaved architecture for the de-blocking filter in H.264. Specifically, to efficiently use the bus bandwidth, we classify the filtering mode into 8 types and use an adaptive transmission scheme to avoid redundant data transfer. Moreover, to reduce the processing latency, we use a bus-interleaved architecture for conducting data transmission and filtering in parallel. As compared to the state-of-the-art designs, our scheme offers 1.6x to 7x performance improvement. While clocking at 100MHz, our design can support 2560x1280@30Hz processing throughput. The proposed design is suitable for low cost and real-time applications. Moreover, it can be easily applied in system-on-chip design.
引用
收藏
页码:249 / 255
页数:7
相关论文
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CHANG SC, 2005, IEEE INT C CONS EL
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Huang Y., 2003, IEEE INT C MULT EXP
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IEEE TRANSACTIONS ON CONSUMER ELECTRONICS, 2004, 50 (01) :292-296
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