Parallel processing addition and subtraction using binary coded redundant positive-digit number representation

被引：0

作者：

Tabata, T ^{[1
]}

Ueno, F ^{[1
]}

Inoue, T ^{[1
]}

机构：

[1] Kumamoto Natl Coll Technol, Kumamoto 8611102, Japan

来源：

APCCAS '98 - IEEE ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS: MICROELECTRONICS AND INTEGRATING SYSTEMS | 1998年

关键词：

D O I：

10.1109/APCCAS.1998.743901

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The redundantly-represented positive-digit number addition is one of the most effective method in making digital addition circuit at higher speed. In this paper, a new voltage-mode multiple-radix parallel processing addition circuit using positive redundantly-expressed binary-coded numbers is discussed.

引用

页码：639 / 642

页数：4

共 13 条

[1] Avizienis A, 1961, IRE Trans Electron Comput EC, VEC-10, P389, DOI DOI 10.1109/TEC.1961.5219227
[2] HIGH-SPEED AREA-EFFICIENT MULTIPLIER DESIGN USING MULTIPLE-VALUED CURRENT-MODE CIRCUITS
KAWAHITO, S
ISHIDA, M
NAKAMURA, T
KAMEYAMA, M
HIGUCHI, T
[J]. IEEE TRANSACTIONS ON COMPUTERS, 1994, 43 (01) : 34 - 42
[3] KAWAHITO S, 1993, IEICE T ELECTRON, VE76C, P446
[4] MULTIPLE-VALUED RADIX-2 SIGNED-DIGIT ARITHMETIC CIRCUITS FOR HIGH-PERFORMANCE VLSI SYSTEMS
KAWAHITO, S
KAMEYAMA, M
HIGUCHI, T
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1990, 25 (01) : 125 - 131
[5] A 32X32-BIT MULTIPLIER USING MULTIPLE-VALUED MOS CURRENT-MODE CIRCUITS
KAWAHITO, S
KAMEYAMA, M
HIGUCHI, T
YAMADA, H
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1988, 23 (01) : 124 - 132
[6] KUNINOBU S, 1993, IEICE T ELECTRON, VE76C, P436
[7] A BICMOS DYNAMIC CARRY LOOKAHEAD ADDER CIRCUIT FOR VLSI IMPLEMENTATION OF HIGH-SPEED ARITHMETIC UNIT
KUO, JB
LIAO, HJ
CHEN, HP
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1993, 28 (03) : 375 - 378
[8] A BICMOS DYNAMIC CARRY LOOK-AHEAD CIRCUIT WITH CARRY SKIP FOR HIGH-SPEED ARITHMETIC CIRCUITS
KUO, JB
LIAO, HJ
CHEN, HP
[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 1992, 39 (12): : 869 - 871
[9] Manzoul M. A., 1988, Proceedings of the Eighteenth International Symposium on Multiple-Valued Logic (Cat. No.88CH2546-0), P294, DOI 10.1109/ISMVL.1988.5186
[10] Tabata T, 1997, IEICE T FUND ELECTR, VE80A, P1002

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