Digital circuit capacitance and switching analysis for ground bounce in ICs with a high ohmic substrate

被引：4

作者：

Badaroglu, M ^{[1
]}

Balasubramanian, L ^{[1
]}

Tiri, K ^{[1
]}

Gravot, V ^{[1
]}

Wambacq, P ^{[1
]}

Van der Plas, G ^{[1
]}

Donnay, S ^{[1
]}

Gielen, G ^{[1
]}

De Man, H ^{[1
]}

机构：

[1] IMEC, DESICS, B-3001 Louvain, Belgium

来源：

ESSCIRC 2003: PROCEEDINGS OF THE 29TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE | 2003年

关键词：

D O I：

10.1109/ESSCIRC.2003.1257121

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Ground bounce is a major contributor to substrate noise generation due to the resonance caused by the inductance and the VDD-VSS admittance that consists of the on-chip digital circuit capacitance of the MOS transistors, the decoupling, and the parasitics arising from the interconnect. This paper addresses (1) the dependence of the VDD-VSS admittance on the different states of the circuit and the interconnect and (2) the computation of total supply current with ground bounce. The VDD-VSS admittances of several test circuits are computed with 13% maximum error relative to the measurements on a test ASIC fabricated in a 0.18mum CMOS process on a high-ohmic substrate with 18Omegacm resistivity. It is also shown that this admittance depends on the connectivity of the gates to the supply rail rather than their connectivity among each other.

引用

页码：257 / 260

页数：4

共 7 条

[1] Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits [J].