Hardware implementation of N-LUT method using Field Programmable Gate Array technology

被引：5

作者：

Kwon, Do-woo ^{[1
]}

Kim, Seung-Cheol ^{[1
]}

Kim, Eun-Soo ^{[1
]}

机构：

[1] Kwangwoon Univ, Display Res Ctr 3D, Dept Elect Engn, Seoul 139701, South Korea

来源：

PRACTICAL HOLOGRAPHY XXV: MATERIALS AND APPLICATIONS | 2011年 / 7957卷

关键词：

Computer generated hologram; Novel look-up table; FPGA;

D O I：

10.1117/12.876616

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Hardware implementation for holographic 3D display application is researched by many researchers. Therefore, in this paper, we propose the hardware implementation method for novel look-up table (N-LUT) method using Field Programmable Gate Array (FPGA) technology. In the proposed method, calculation process is divided by some segment block for fast parallel processing of calculation of N-LUT method. That is, by using parallel processing by use of some segmented block based on FPGA technology, calculation speed of CGH can be increased

引用

页数：8

共 4 条

[1] Special-purpose computer HORN-5 for a real-time electroholography [J].

Ito, T ;

Masuda, N ;

Yoshimura, K ;

Shiraki, A ;

Shimobaba, T ;

Sugie, T .

OPTICS EXPRESS, 2005, 13 (06) :1923-1932

[2]

Kim Jae-Man, 2010, MEMORY REDUCTION NOV, P205

[3] Effective generation of digital holograms of three-dimensional objects using a novel look-up table method [J].

Kim, Seung-Cheol ;

Kim, Eun-Soo .

APPLIED OPTICS, 2008, 47 (19) :D55-D62

[4]

Lucente M., 1993, Journal of Electronic Imaging, V2, P28, DOI 10.1117/12.133376

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