Design of High Performance Multiply-Accumulate Computation Unit

被引：0

作者：

Ahish, S. ^{[1
]}

Kumar, Y. B. N. ^{[1
]}

Sharma, Dheeraj ^{[1
]}

Vasantha, M. H. ^{[1
]}

机构：

[1] Natl Inst Technol Goa, Dept Elect & Commun, Veling, India

来源：

2015 IEEE INTERNATIONAL ADVANCE COMPUTING CONFERENCE (IACC) | 2015年

关键词：

Carry-lookahead adder; brent-kung adder; wallace tree; booth multiplier; multiply-accumulate unit;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

In Digital Signal Processing (DSP), Multiply-Accumulate Computation (MAC) unit plays a very important role and lies in the critical path. Multiplier is one of the most important block in MAC unit. The overall performance of the MAC unit depends on the resources used by the multiplier. Therefore, this paper describes the design of a Partial Product Reduction Block (PPRB) that is used in the implementation of multiplier having better area, delay and power performances. PPRB reduces the partial products row wise by using different multi-bit adder blocks instead of conventional coloumn wise reduction. MAC unit consisting of the multiplier realized using the proposed partial product reduction technique has a delay reduction of 46%, power consumption is reduced by 39% and area requirement is reduced by 17% when compared to MAC unit realised using conventional multiplier architecture.

引用

页码：915 / 918

页数：4

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