On statistical timing analysis with inter- and intra-die variations

被引：13

作者：

Mangassarian, H ^{[1
]}

Anis, M ^{[1
]}

机构：

[1] Univ Waterloo, ECE Dept, Waterloo, ON N2L 3G1, Canada

来源：

DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS | 2005年

关键词：

D O I：

10.1109/DATE.2005.226

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper we highlight a fast, effective and practical statistical approach that deals with inter and intra-die variations in VLSI chips. Our methodology is applied to a number of random variables while accounting for spatial correlations. Our methodology sorts the Probability Density Functions (PDFs) of the critical paths of a circuit based on a confidence-point. We show the mathematical accuracy of our method as well as implement a typical program to test it on various benchmarks. We find that worst-case analysis overestimates path delays by more than 50% and that a path's probabilistic rank with respect to delay is very different from its deterministic rank.

引用

页码：132 / 137

页数：6

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