Non-intrusive BIST for systems-on-a-chip

被引:18
作者
Chiusano, S [1 ]
Prinetto, P [1 ]
Wunderlich, HJ [1 ]
机构
[1] Politecn Torino, Dipartimento Automat Informat, I-10129 Turin, Italy
来源
INTERNATIONAL TEST CONFERENCE 2000, PROCEEDINGS | 2000年
关键词
D O I
10.1109/TEST.2000.894259
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
The term "functional BIST" describes a test method to control functional modules so that they generate a deterministic test set, which targets structural faults within other parts of the system. It is a promising solution for self-testing complex digital systems at reduced costs in terms of area overhead and performance degradation. While previous work mainly investigated the use of functional modules for generating pseudo-random and pseudo-exhaustive rest patterns, the present paper shows that a variety of modules can also be used as a deterministic test pattern generator via an appropriate reseeding strategy. This method enables a BIST technique that does nor introduce additional hardware like test points and test registers into combinational and pipelined modules under rest. The experimental results prove that the reseeding method works for accumulator based structures, multipliers, or encryption modules as efficiently as for the classic linear feedback shift registers, and sone times even better.
引用
收藏
页码:644 / 651
页数:8
相关论文
共 28 条
  • [1] [Anonymous], ARITHMETIC BUILT SEL
  • [2] Brglez F., 1989, International Test Conference 1989. Proceedings. Meeting the Tests of Time (Cat. No.89CH2742-5), P264, DOI 10.1109/TEST.1989.82307
  • [3] Brglez F, 1985, IEEE INT S CIRC SYST
  • [4] CATALDO S, 2000, OPTIMAL HARDWARE PAT, P292
  • [5] CHENG KT, 1995, IEEE INT TEST C, P506
  • [6] Cellular automata for deterministic sequential test pattern generation
    Chiusano, S
    Corno, F
    Prinetto, P
    Reorda, MS
    [J]. 15TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 1997, : 60 - 65
  • [7] DORSCH R, 1999, IEEE INT TEST C
  • [8] Goldberg D. E., 1989, GEN ALG SEARCH OPT M
  • [9] Arithmetic additive generators of pseudo-exhaustive test patterns
    Gupta, S
    Rajski, J
    Tyszer, J
    [J]. IEEE TRANSACTIONS ON COMPUTERS, 1996, 45 (08) : 939 - 949
  • [10] GUPTA S, 1994, IEEE INT C COMP AID