Design of low power current-mode flash ADC

被引：0

作者：

Bhat, MS ^{[1
]}

Rekha, S ^{[1
]}

Jamadagni, HS ^{[1
]}

机构：

[1] Indian Inst Sci, Ctr Elect Design & Technol, Bangalore 560012, Karnataka, India

来源：

TENCON 2004 - 2004 IEEE REGION 10 CONFERENCE, VOLS A-D, PROCEEDINGS: ANALOG AND DIGITAL TECHNIQUES IN ELECTRICAL ENGINEERING | 2004年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

The design of a high-speed current-mode CMOS flash analog-to-digital converter (ADC) is presented For high-speed operation, current mirroring technique with current comparison architecture is used and its advantages and limitations are explained. The optimization procedure is aimed at minimizing static power consumption, and its impact on circuit performance is investigated. A maximum sampling speed of 80Ms/sec is achieved at 78mW power consumption. The ADC is designed using 0.7-mu m CMOS technolog.

引用

页码：D241 / D244

页数：4

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