Variability and Soft-error Resilience in Dependable VLSI Platform

被引：0

作者：

Mitsuyama, Yukio ^{[1
]}

Onodera, Hidetoshi ^{[2
]}

机构：

[1] Kochi Univ Technol, Dept Elect Engn, Kami, Japan

[2] Kyoto Univ, Dept Commun & Comp Engn, Kyoto, Japan

来源：

2014 IEEE 23RD ASIAN TEST SYMPOSIUM (ATS) | 2014年

关键词：

dependable; robust; variability; monitoring; compensation; reconfigurable architecture; soft error; radiation test; RECONFIGURABLE ARCHITECTURE; FLIP-FLOP; DESIGN;

D O I：

10.1109/ATS.2014.20

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Extreme scaling imposes enormous challenges, such as variability increase and soft-error vulnerability, on the resilience of VLSI circuits and systems. For coping with those threats, we have been developing a VLSI platform that can realize a dependable circuit with required level of reliability. In the platform, circuit-level resilience to variability is achieved by on-chip performance monitoring and variability compensation by localized body biasing. Architecture-level resilience to soft-errors is accommodated by a mixed-grained reconfigurable array in which functionality as well as reliability can be configured. Those properties have been experimentally verified by proof-of-concept chips in 65nm process. Overview of the variability and soft-error resilience of the platform will be explained, followed by experimental demonstrations.

引用

页码：45 / 50

页数：6

共 50 条

[41] A Soft-Error Hardened Process Portable Embedded Microprocessor
Vashishtha, Vinay
Clark, Lawrence T.
Chellappa, Srivatsan
Gogulamudi, Anudeep R.
Gujja, Aditya
Farnsworth, Chad
2015 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2015,
[42] CELL DESIGN CUTS RAM SOFT-ERROR RATE
LEONARD, M
ELECTRONIC DESIGN, 1988, 36 (19) : 29 - 29
[43] Asymmetries in soft-error rates in a large cluster system
Harris, KW
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2005, 5 (03) : 336 - 342
[44] Improving soft-error tolerance of FPGA configuration bits
Srinivasan, S
Gayasen, A
Vijaykrishnan, N
Kandemir, M
Xie, Y
Irwin, MJ
ICCAD-2004: INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, IEEE/ACM DIGEST OF TECHNICAL PAPERS, 2004, : 107 - 110
[45] Soft-Error Hardening Designs of Nanoscale CMOS Latches
Lin, Sheng
Kim, Yong-Bin
Lombardi, Fabrizio
2009 27TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2009, : 41 - 46
[46] Generation of stressmarks for early stage soft-error modeling
Swaminathan, Karthik
Bertran, Ramon
Jacobson, Hans
Kudva, Prabhakar
Bose, Pradip
2019 49TH ANNUAL IEEE/IFIP INTERNATIONAL CONFERENCE ON DEPENDABLE SYSTEMS AND NETWORKS - SUPPLEMENTAL VOL (DSN-S), 2019, : 42 - 48
[47] Generic Soft-Error Detection and Correction for Concurrent Data Structures
Borchert, Christoph
Schirmeier, Horst
Spinczyk, Olaf
IEEE TRANSACTIONS ON DEPENDABLE AND SECURE COMPUTING, 2017, 14 (01) : 22 - 36
[48] A Method to Detect Bit Flips in a Soft-Error Resilient TCAM
Syafalni, Infall
Sasao, Tsutomu
Wen, Xiaoqing
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2018, 37 (06) : 1185 - 1196
[49] Real-time soft-error rate measurements: A review
Autran, J. L.
Munteanu, D.
Roche, P.
Gasiot, G.
MICROELECTRONICS RELIABILITY, 2014, 54 (08) : 1455 - 1476
[50] Performance and Accuracy in Soft-Error Resilience Evaluation using the Multi-Level Processor Simulator ETISS-ML
Mueller-Gritschneder, Daniel
Sharif, Uzair
Schlichtmann, Ulf
2018 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD) DIGEST OF TECHNICAL PAPERS, 2018,

← 1 2 3 4 5 →