Variability and Soft-error Resilience in Dependable VLSI Platform

Extreme scaling imposes enormous challenges, such as variability increase and soft-error vulnerability, on the resilience of VLSI circuits and systems. For coping with those threats, we have been developing a VLSI platform that can realize a dependable circuit with required level of reliability. In the platform, circuit-level resilience to variability is achieved by on-chip performance monitoring and variability compensation by localized body biasing. Architecture-level resilience to soft-errors is accommodated by a mixed-grained reconfigurable array in which functionality as well as reliability can be configured. Those properties have been experimentally verified by proof-of-concept chips in 65nm process. Overview of the variability and soft-error resilience of the platform will be explained, followed by experimental demonstrations.