Optimizing Multi-Constraint VLSI Interconnect Routing

Buffer insertion and wire-sizing in Very Large Scale Integrated Circuit interconnect routing are multi-constraint optimization problem, optimizing constraints such as delay, skew, area, and power. This paper proposes a multi-constraint VLSI interconnect routing technique, called MCRouting, that optimizes different constraints such as delay and buffer area through simultaneous wire-sizing and buffer insertions. A look-ahead method is used to simultaneously estimate the constraints of several routes. The principle of non-dominance is used to minimize routing search space. Path length method is used to select routes within predefined constraint bounds. Simulation results show than the proposed technique could handle multiple routing constraints. However, it requires longer simulation time compared to single-constraint routing with the total time in order of seconds.