A Low-Cost and Low-Power Time-to-Digital Converter Using Triple-Slope Time Stretching

被引：19

作者：

Kim, Manho ^{[1
]}

Lee, Hyunjoong ^{[2
]}

Woo, Jong-Kwan ^{[2
]}

Xing, Nan ^{[1
]}

Kim, Min-Oh ^{[2
]}

Kim, Suhwan ^{[2
]}

机构：

[1] Seoul Natl Univ, Dept Elect Engn, Seoul 151742, South Korea

[2] Seoul Natl Univ, Dept Elect Engn, Seoul 151744, South Korea

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2011年 / 58卷 / 03期

关键词：

Dual-slope conversion; interpolator; time stretcher; time-to-digital converter (TDC); CMOS; PRECISION;

D O I：

10.1109/TCSII.2011.2106353

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this brief, we present a time-to-digital converter (TDC) in which a single interpolator is used to improve the resolution by time stretching. The interpolator is based on a triple-slope conversion. Without slowing down the measured event, this approach extensively reduces the chip area and the corresponding power consumption, as compared with the prior arts with two parallel time interpolators. A prototype was designed and fabricated in a 0.35-mu m CMOS digital process, and its core area merely occupies 0.126 mm(2). Measurements show that our TDC achieves a resolution of 357 ps while consuming 1.22m W with a 2.5-V supply. The dynamic range of the TDC exceeds 1.46 mu s. The measurement rate can achieve above 400 kS/s.

引用

页码：169 / 173

页数：5

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