Combined transistor sizing with buffer insertion for timing optimization

被引：0

作者：

Jiang, YB ^{[1
]}

Sapatnekar, SS ^{[1
]}

Bamji, C ^{[1
]}

Kim, JH ^{[1
]}

机构：

[1] Iowa State Univ, Dept ECE, Ames, IA 50011 USA

来源：

IEEE 1998 CUSTOM INTEGRATED CIRCUITS CONFERENCE - PROCEEDINGS | 1998年

关键词：

D O I：

10.1109/CICC.1998.695051

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents strategies to insert buffers in a circuit, combined with gate sizing, to achieve better power-delay and area-delay tradeoffs. The delay model incorporates placement-based information and the effect of input slew rates on gate delays. The results obtained by using the new method are significantly better than the results given by merely using a TILOS-like transistor sizing algorithm alone.

引用

页码：605 / 608

页数：4