LOW POWER ENCODER FOR FLASH ADC ARCHITECTURE

被引：0

作者：

Sindhuja, R. ^{[1
]}

Navaneethakrishnan, V. ^{[1
]}

Kavitha, A. ^{[1
]}

机构：

[1] Chettinad Coll Engn & Technol, Dept ECE, Karur, India

来源：

PROCEEDINGS OF THE 10TH INDIACOM - 2016 3RD INTERNATIONAL CONFERENCE ON COMPUTING FOR SUSTAINABLE GLOBAL DEVELOPMENT | 2016年

关键词：

FADC; Encoder; Full Adder; Low power;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

In this paper emphasize tremendous speed and low power design of an encoder for Flash A/D converter (FADC). Analog and digital signals are used to transmit information through the electrical signals. The proposed technique has been designed for better implementation of system on chip application. It will improve the performance by reducing the propagation delay and area. The proposed architecture simulated using cadence virtuoso 180nm CMOS Technology at 1.8V supply voltage.

引用

页码：1521 / 1524

页数：4

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