A new cycle-time-to-digital converter with two level conversion scheme

被引：7

作者：

Huang, Hong-Yi ^{[1
]}

Wu, Sheng-Da ^{[2
]}

Tsai, Yi-Jui ^{[3
]}

机构：

[1] Natl Taipei Univ, Grad Inst Elect Engn, Taipei, Taiwan

[2] Fu Jen Catholic Univ, Dept Elect Engn, Taipei 493506235, Taiwan

[3] Fu Jen Catholic Univ, Dept Elect Engn, Taipei 493506239, Taiwan

来源：

2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11 | 2007年

关键词：

D O I：

10.1109/ISCAS.2007.378601

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This work presents a CMOS cycle time-to-digital converter (CDC) integrated circuit utilizing a two-level conversion scheme. The technique that allows the achievement of wide dynamic range is presented. The CDC is based on a multi-phase sampling and vernier delay line (VDL) used in conjunction with a synchronous read-out circuitry. The proposed CDC can provide high resolution with the high conversion rate. The CDC achieves 83.3 MEvents/sec conversion rate and 23-ps resolution, stabilized by the dual DLL. The DNL is less than +/- 0.34 LSB (23 ps). The INL is +/- 0.33 LSB.

引用

页码：2160 / +

页数：2

共 5 条

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